1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a conductive layer contact structure for a conductive region formed at the surface of a semiconductor substrate between the conductive layers formed on the semiconductor substrate and a method of manufacturing the same.
2. Description of the Background Art
Recently, as can be seen from the fact that DRAMs (Dynamic Random Access Memories) and the like are becoming integrated to a higher degree, degree of integration of semiconductor devices is being made higher, and thus dimension of the diameters of the contact holes is becoming more and more reduced as a result of increase in degree of integration of the elements incorporated into the semiconductor devices. In order to form a smaller contact hole, polycrystalline silicon mask opening method and self align contact (SAC) opening method are being considered.
FIG. 26 is a partial cross sectional view of a semiconductor device, showing a contact hole formed by polycrystalline silicon mask opening method at a memory device region of a semiconductor device. Referring to FIG. 26, an isolation oxide film 2 is formed at the surface of a p type polycrystalline silicon substrate 1 by the method of LOCOS (Local Oxidation of Silicon). On the surfaces of p type silicon substrate 1 and isolation oxide film 2, gate oxide films 3 are formed. A gate electrode 4 is formed on this gate oxide film 3. An insulation film 5 is formed on gate electrode 4. On the surface of p type silicon substrate 1 at both sides of gate electrode 4, nxe2x88x92 diffused regions 6 containing an n type impurity of low concentration are formed by the method of LDD (Lightly Doped Drain). At the side surfaces of gate oxide film 3, gate electrode 4 and insulation film 5, sidewall spacers 7 are formed as insulation films. In addition, an n+ diffused layer 8 containing n type impurity of high concentration is formed at the surface of p type silicon substrate 1 so as to join nxe2x88x92 diffused regions 6. Covering gate electrode 4, an interlayer insulation film 11 of silicon oxide film is formed on the surface of p type silicon substrate 1, employing TEOS (Tetraethyl Orthosilicate) as the material. In this interlayer insulation film 11, a contact hole 105 of a small diameter is formed by etching interlayer insulation film 11 to reach a portion of the surface of n+ diffused layer 8.
Description will be made for a method of forming the contact hole shown in FIG. 26, with reference to FIGS. 27A to 27B and 27B to 30B.
FIGS. 27A to 30A are partial cross sectional views illustrating the process of forming the contact hole shown in FIG. 26 at the memory device region in the order of the steps performed. FIGS. 27B to 30B are partial cross sectional views illustrating the process of forming the contact hole shown in FIG. 26 at the peripheral circuit region in the order of the steps performed.
Referring to FIGS. 27A and FIG. 27B, isolating oxide film 2, gate oxide film 3, gate electrode 4, insulation film 5, nxe2x88x92 diffused layer 6, sidewall spacer 7, n+ diffused layer 8 and interlayer insulation film 11 having a thickness of 3000 to 4000 xc3x85 are formed on p type silicon substrate 1. Thereafter, a polycrystalline silicon film 101 having a thickness of 1500 to 3000 xc3x85 is deposited on the entire surface of the interlayer insulation film, and a silicon oxide film 102 employing TEOS as its material (hereinafter referred to as xe2x80x9cTEOS oxide filmxe2x80x9d) is further deposited thereon. On this TEOS oxide film 102, a resist (not shown) is formed, and using the patterned resist as a mask, TEOS oxide film 102 is partially etched. Thus, a hole 103a having a diameter of about 0.3 xcexcm is formed to reach the surface of polycrystalline silicon film 101. Then, on the entire surface of TEOS oxide film 102, a TEOS oxide film is deposited again. By etching back the entire surface of this TEOS oxide film with anisotropical etching, a sidewall spacer 103 of TEOS oxide film is formed at the inner sidewall of hole 103a which had been formed at TEOS oxide film 102.
Thereafter, as shown in FIGS. 28A and 28B, polycrystalline silicon film 101 is etched using TEOS oxide film 102 and sidewall spacer 103 as a mask so as to form a hole 104 having a diameter of 0.08 to 0.12 xcexcm. Then, TEOS oxide film 102 and sidewall spacer 103 are etched away.
Then, referring to FIGS. 29A and 29B, polycrystalline silicon film 101 is used as a mask to etch interlayer insulation layer 11 thereby forming a contact hole 105 with a small diameter. Thereafter, as shown in FIGS. 30A and 30B, polycrystalline silicon film 101 is removed by having its surface entirely subjected to etching. Thus, the contact hole shown in FIG. 26 is formed.
When forming a contact hole with polycrystalline silicon mask opening method as described above, there has been the following problems. First of all, when a contact hole of a small diameter having a high aspect ratio, for example, not lower than 4, is formed at interlayer insulation layer 11, the etching rate would be extremely low, and thus it was very difficult to open a contact hole by an accurate etching. In addition, since it is difficult to bury the material of the conductive layer inside the contact hole after the contact hole is formed, it was difficult to form a conductive layer along the inner sidewall of the contact hole such that a satisfactory step coverage is obtained. Accordingly, there has been problems such as disconnection of conductive layer 106 and increase in contact resistance between conductive layer 106 and n+ diffused layer 8, as shown in FIG. 31.
Moreover, in the case of forming a contact hole with polycrystalline silicon mask opening method, when etching back the entire surface of polycrystalline silicon film 101, there has been a problem that etching is performed at the peripheral circuit region until the surface of gate electrode 4 is exposed, as shown in FIG. 30B. This is because the thickness of interlayer insulation layer 11 covering the surface of gate electrode 4 is thin due to the wide interval between the gate electrodes.
FIG. 32 is a partial cross sectional view showing a semiconductor device having a contact hole formed by self align contact opening method. Referring to FIG. 32, a gate oxide film 3 is formed on the surface of a p type silicon substrate 1. A gate electrode 4 is formed on gate oxide film 3. An insulation film 5 is formed on gate electrode 4. Nxe2x88x92 diffused regions 6 are formed at the surface of p type silicon substrate 1 at both sides of gate electrode 4 by the method of LDD. Sidewall spacer 7 is formed at the side surface of gate oxide film 3, gate electrode 4 and insulation film 5. N+ diffused regions 8 are formed at the surface of p type silicon substrate 1 so as to join nxe2x88x92 diffused layers 6. Silicon oxide film 9 is formed on the surface of p type silicon substrate 1 covering insulation film 5 and sidewall spacer 7. A silicon nitride film 10 is formed on silicon oxide film 9.
Moreover, an interlayer insulation layer 11 of TEOS oxide film is formed on silicon nitride film 10. Contact hole 110 is formed to penetrate silicon oxide film 9, silicon nitride film 10 and interlayer insulation layer 11 to reach a portion of the surface of n+ diffused layer 8. A polycrystalline silicon layer 17 and a tungsten silicide layer 18 are formed as a conductive layer for being in electrical connection with n+ diffused layer 8 via contact hole 110. This conductive layer has two-layered structure including polycrystalline silicon 17 and tungsten silicide 18 to reduce interconnection resistance.
Referring next to FIGS. 33 to 36, description is made for a method of forming the contact hole of FIG. 32. FIGS. 33 to 36 are partial cross sectional views illustrating the process of forming the contact hole of FIG. 32 in the order of the steps performed.
Referring to FIG. 33, gate oxide film 3, gate electrode 4, insulation film 5, sidewall spacer 7, nxe2x88x92 diffused layer 6, n+ diffused layer 8, silicon oxide film 9, silicon nitride film 10 and interlayer insulation film 11 are formed on p type silicon substrate 1. Thereafter, a resist film 107 is formed on interlayer insulation film 11, and a hole 108 is opened at resist film 107.
Then, as shown in FIG. 34, interlayer insulation film 11 is subjected to etching using resist film 107 (FIG. 33) as a mask, thereby forming a hole 109. Resist film 107 is then removed.
Thereafter, as shown in FIG. 35, by etching silicon nitride film 10 and silicon oxide film 9 successively, a contact hole 110 is opened.
Then, as shown in FIG. 36, polycrystalline silicon layer 17 and tungsten silicide layer 18 are formed as conductive layers so as to be electrically connected to n+ diffused layer 8 via contact hole 110. Thus, the contact hole is formed with self align contact opening method, and the conductive layer contact structure is formed.
When the contact hole is formed by self align contact opening method as describe above, the diameter of contact hole 110 would be about 0.30 xcexcm and the distance between the gate electrodes 4 would be 0.32 to 0.36 xcexcm, such that there would be a higher possibility that locations of contact hole 110 and gate electrode below may be overlapped. If the locations of contact hole 110 and gate electrode 4 is overlapped, a contact hole would be formed as shown in FIG. 37, and a conductive layer contact structure as shown in FIG. 38 would be formed. In such a case, when silicon oxide film 9 is over etched due to uniformity of the etching inside the surface upon opening contact hole 110, insulation film 5 and sidewall spacer 7 are subjected to etching, as shown in FIG. 39. As a result, there has been a problem that polycrystalline silicon layer 17 forming the conductive layer and gate electrode 4 is brought into contact and are electrically short-circuited. In addition, since in self align contact opening method a resist patterned by photolithography technique is used as a mask to etch interlayer insulation layer 11 as shown in FIGS. 33 to 35, it was impossible to form a contact hole having a diameter smaller than the resolution of the photolithography technique.
One object of the present invention is to form a contact hole having a diameter smaller than the resolution of the photolithography technique.
In addition, another object of the present invention is to form a contact hole with a desired size in a stabilized manner by etching involving a low aspect ratio.
Furthermore, another object of the present invention is to form a contact hole in which a conductive layer connected to a conductive region of a semiconductor substrate via the contact hole will not be electrically short-circuited to a conductive layer below.
A further object of the present invention is to form a conductive layer contact structure having a low contact resistance.
A still further object of the present invention is to form a conductive layer contact structure in which the step coverage of the conductive layer is satisfactory at the inner sidewall of a contact hole.
In addition, a further object of the present invention is to improve the alignment margin upon forming a contact hole.
A semiconductor device having a conductive layer contact structure according to one aspect of the present invention includes a first conductive layer, a conductive region, a first insulation layer, a second insulation layer, a sidewall insulation layer and a second conductive layer. The first conductive layer is formed on a main surface of a semiconductor substrate. The conductive region is formed at the main surface of the semiconductor substrate between the first conductive layers. The first insulation layer has a first hole reaching the surface of the conductive region, and is formed on the first conductive layer. The second insulation layer has a second hole in communication with the first hole, is formed on the first insulation layer and has a high etching selectivity with respect to the first insulation layer. The sidewall insulation film is formed at the inner sidewall of the second insulation layer defining the second hole. The second conductive layer is formed within the first and second holes such that it is in electrical connection with the conductive region and is electrically insulated from the first conductive layer.
Preferably, the sidewall insulation film has a high etching selectivity with respect to the first insulation layer.
In addition, in accordance with a preferred embodiment of the present invention, the first insulation layer includes upper and lower insulation layers, and the second insulation layer has a high etching selectivity with respect to the upper insulation layer of the first insulation layer. Here, it is preferred that the sidewall insulation film has a high etching selectivity with respect to the upper insulation layer of the first insulation layer. In addition, the first hole is defined by the inner sidewall of the lower insulation layer of the first insulation layer while the second hole is defined by the inner sidewall of the upper insulation layer of the first insulation layer and the inner sidewall of the second insulation layer. The sidewall insulation film is formed at the inner sidewall of the upper insulation layer of the first insulation layer and the inner sidewall of the second insulation layer. The second hole includes a third hole defined by the inner sidewall of the upper insulation layer of the first insulation layer and a fourth hole smaller than the third hole defined by the inner sidewall of the second insulation layer.
The semiconductor device having a conductive layer contact structure according to another aspect of the present invention includes a first conductive layer, a conductive region, a first insulation layer, a second insulation layer and a second conductive layer. The first conductive layer is formed on a main surface of a semiconductor substrate. The conductive region is formed at the main surface of the semiconductor substrate between the first conductive layers. The first insulation layer has a first hole reaching the surface of the conductive region, and is formed on the first conductive layer. The second insulation layer has a second hole larger than the first hole which is in communication with the first hole, is formed on the first insulation layer, and has a high etching selectivity with respect to the first insulation layer. The second conductive layer is formed within the first and second holes so as to be electrically connected to the conductive region and to be electrically insulated from the first conductive layer.
In accordance with the above-described preferred embodiment of the invention, the first insulation layer includes upper and lower insulation layers, and the second insulation layer has a high etching selectivity with respect to the upper insulation layer of the first insulation layer. Here, an additional sidewall insulation film may also be formed at the inner sidewall of the second insulation layer defining the second hole. It is preferred that this sidewall insulation film has a high etching selectivity with respect to the upper insulation layer of the first insulation layer.
In addition, in accordance with another preferred embodiment of the present invention, a sidewall insulation film is additionally formed at the inner sidewall of the second insulation layer defining the second hole, and this sidewall insulation film has a high etching selectivity with respect to the first insulation layer.
In addition, the conductive layer contact structure according to the present invention is also applicable to the case in which the second hole exists at a location overlapping a portion of the first conductive layer.
A method of manufacturing a semiconductor device having a conductive layer contact structure according to another aspect of the present invention includes the following steps:
(a) forming a first conductive layer on a main surface of a semiconductor substrate;
(b) forming a conductive region at the main surface of the semiconductor substrate between the first conductive layers;
(c) forming a first insulation layer on the main surface of the semiconductor substrate and on the first conductive layer;
(d) forming the second insulation layer having a high etching selectivity with respect to the first insulation layer on the first insulation layer;
(e) forming a first hole reaching the surface of the first insulation layer in the second insulation layer by selectively removing the second insulation layer;
(f) forming a third insulation layer on the second insulation layer and within the first hole;
(g) forming a sidewall insulation film at the inner sidewall of the second insulation layer defining the first hole by selectively removing the third insulation layer;
(h) forming a second hole reaching the surface the conductive region in the first insulation layer by selectively removing the first insulation layer using the sidewall insulation film as a mask; and
(i) forming a second conductive layer within the first and second holes such that it is electrically connected to the conductive,region and is electrically insulated from the first conductive layer.
According to a preferred embodiment of a manufacturing method of the above-described semiconductor device, the step of forming the first insulation layer includes forming a first insulation layer including upper and lower insulation layers on the main surface of the semiconductor substrate and on the first insulation layer. The step of forming the second insulation layer includes forming on the first insulation layer a second insulation layer having a high etching selectivity with respect to the upper insulation layer of the first insulation layer. Furthermore, the step of forming the second hole in the first insulation layer includes forming a hole in the upper insulation layer of the first insulation layer to reach the surface of the lower insulation layer of the first insulation layer by selectively removing the upper insulation layer of the first insulation layer using the sidewall insulation film as a mask, and forming a hole in the lower insulation layer of the first insulation layer to reach the surface of the conductive region by selectively removing the lower insulation layer of the first insulation layer using the upper insulation layer of the first insulation layer as a mask.
In addition, according to the above-described preferred embodiment of the manufacturing method of the semiconductor device in accordance with the invention, the step of forming the first insulation layer includes forming a first insulation layer including upper and lower insulation layers on the main surface of the semiconductor substrate and on the first conductive layer. Moreover, the step of forming the second insulation layer includes forming a second insulation layer having a high etching selectivity with respect to the upper insulation layer of the first insulation layer on the first insulation layer. Furthermore, the manufacturing method of the semiconductor device according to this preferred embodiment includes the step of forming a third hole in the upper insulation layer of the first insulation layer to reach the surface of the lower insulation layer of the first insulation layer by selectively removing the upper insulation layer of the first insulation layer after forming the first hole in the second insulation layer. The step of forming the third insulation layer includes forming a third insulation layer on the second insulation layer and within the first and third holes. The step of forming the sidewall insulation film includes forming a sidewall insulation film at the inner sidewall of the second insulation layer defining the first hole and the inner sidewall of the upper insulation layer of the first insulation layer defining the third hole by selectively removing the third insulation layer. The step of forming the second hole in the first insulation layer includes forming the second hole reaching the surface of the conductive region in the lower insulation layer of the first insulation layer by selectively removing the lower insulation layer of the first insulation layer using the sidewall insulation film as a mask. The step of forming the second conductive layer includes forming a second conductive layer inside the first, second and third holes.
The manufacturing method of the semiconductor device according to the above-described invention is also applicable to the case in which the first hole exists at a location overlapping a portion of the first conductive layer.
A method of manufacturing a semiconductor device having a conductive contact structure according to another aspect of the present invention includes the following steps:
(i) forming a first conductive layer on a main surface of a semiconductor substrate;
(ii) forming a conductive region at the main surface of the semiconductor substrate between the first conductive layers;
(iii) forming a first insulation layer including upper and lower insulation layers on the main surface of the semiconductor substrate and on the first conductive layer;
(iv) forming a second insulation layer having a high etching selectivity with respect to the upper insulation layer of the first insulation layer on the first insulation layer;
(v) forming a first hole reaching the surface of the first insulation layer in the second insulation layer by selectively removing the second insulation layer;
(vi) forming a third insulation layer having a high etching selectivity with respect to the upper insulation layer of the first insulation layer and having an etching rate different from that of the second insulation layer on the second insulation layer and within the first hole;
(vii) forming a sidewall insulation film at the inner sidewall of the second insulation layer defining the first hole by selectively removing the third insulation layer;
(viii) forming a second hole reaching the surface of the lower insulation layer of the first insulation layer by selectively removing the upper insulation layer of the first insulation layer using the sidewall insulation film as a mask;
(ix) removing the sidewall insulation film;
(x) forming a third hole in the lower insulation layer of the first insulation layer to reach the surface of the conductive region by selectively removing the lower insulation layer of the first insulation layer using the upper insulation layer of the first insulation layer as a mask; and
(xi) forming a second conductive layer within the first, second and third holes such that it is electrically connected to the conductive region and is electrically insulated from the first conductive layer.
Since a method of forming a contact hole based on self align contact opening method is adopted in the conductive layer contact structure of the present invention formed in this way, a conductive layer contact structure having a low contact resistance can be obtained by an etching with low aspect ratio without the interconnection layer as the second conductive layer being in contact with the gate electrode as the first conductive layer at the peripheral circuit region. In addition, since a sidewall insulation film is formed at the inner sidewall defining the hole of the second insulation layer, a contact hole smaller than the resolution of photolithography technique can be formed to have a desired size in a stabilized manner without the interconnection layer as the second conductive layer being in contact or without being electrically short-circuited with the gate electrode as the first conductive layer at the memory device region also. Furthermore, it is possible to form a second conductive layer with a satisfactory step coverage within the contact hole along the inner sidewall of the contact hole.
Moreover, in a semiconductor device having a conductive layer contact structure according to another aspect of the present invention, the sidewall insulation film is removed in the end within the contact hole, and thus it is possible to obtain a structure having a lower contact hole as compared to the case in which conductive layer contact structure is formed with the sidewall insulation film remaining in the end.
In addition, according to a preferred embodiment of the conductive layer contact structure of the present invention, a sidewall insulation film is formed along the inner sidewall defining the hole of the second insulation layer and the inner sidewall defining the hole of the upper insulation layer of the first insulation layer, and thus the contact hole is tapered forward, in other words, would have its diameter of the opening increased smoothly as it extends upwards from the main surface of the semiconductor substrate. As a result, the step coverage of the second conductive layer formed at the inner sidewall of the contact hole would be satisfactory.
Also, even if the interval between the gate electrodes is wide and the location of the second insulation hole does not overlap the location of the gate electrode below, alignment margin upon formation of the contact hole would be improved as compared to the conventional self align contact opening method.
Thus, according to the present invention, a contact hole with a diameter smaller than the resolution of photolithography technique can be formed by an etching with a low aspect ratio. Even when the upper second conductive layer is formed to be in contact with the conductive region of the semiconductor substrate through that contact hole, it is possible to provide a semiconductor device having a conductive layer contact structure in which the second insulation layer is not electrically short-circuited. Accordingly, a conductive layer contact structure appropriate for a highly integrated semiconductor device such as a bit line contact structure of a DRAM and a storage node contact structure of a capacitor can be provided.